1. Field of the Invention
The present invention generally relates to an analog-to-digital converting system, and more particularly, to an analog-to-digital converting system by using subranging successive approximation (SAR) approach.
2. Description of Related Art
Analog-to-digital converters (ADC) have various architectures, for example, flash analog-to-digital converters (flash ADC), pipeline analog-to-digital converters (pipeline ADC), successive approximation analog-to-digital converters (SA-ADC) and two-steps analog-to-digital converters (two-steps ADC), all of which respectively have suitable application fields.
Flash ADCs are usually used in applications with high sampling rates, but they come with disadvantages of high power consumption. SA-ADCs are limited by lower sampling frequency, but they have advantages of low power consumption and low circuit complicity.
Characteristics of pipeline ADCs are between flash ADCs and SA-ADCs. In particular, pipeline ADCs require to employ multiplier digital-to-analog converters (MDAC), while MDACs include residue operation amplifiers therein, which are characterized by negative feedback architecture. Thus, the residue operation amplifiers appear to be a bottleneck for pipeline ADCs to be used in high speed sampling applications.
Two-steps ADCs can be categorized into bit-cycling analog-to-digital converters (bit-cycling ADC) and subranging analog-to-digital converters (subranging ADC). Bit-cycling ADCs require residue operation amplifiers as well and have problems similar to pipeline ADCs. According to the so far references however, subranging ADCs are capable of breaking through the limitations on pipeline ADCs and two-steps ADCs adopting bit-cycling architecture and capable of reaching high speed sampling.
Several conventional ADC systems are respectively introduced hereinafter.
The first conventional ADC system is disclosed in U.S. Pat. No. 6,124,818, which uses pipeline approach so as to largely enhance the operation capability. In this prior art, a two-steps ADC architecture is adopted, and both the coarse analog-to-digital converter (coarse ADC) and the fine analog-to-digital converter (fine ADC) therein take SA-ADC architecture, so that the resolution demand by the digital-to-analog converter (DAC) is lowered, the circuit area of the DAC gets less and the data-converting speed is advanced. However, due to the coarse ADC is SA-ADC, the first conventional ADC system has long latency and slow sampling frequency.
The second conventional ADC system is disclosed in U.S. Pat. No. 5,973,632, which uses two-steps ADC approach, and both coarse ADC and fine ADC use a flash architecture for converting data so as to advance the data-converting speed of the ADC. Because the fine ADC adopts the flash architecture, the required number of comparators is (2MSBs+2LSBs−2) where MSBs and LSBs respectively represent a most-significant-bit set and a least-significant-bit set. Thus, the second conventional ADC system is disadvantageous in high quantity of the comparators, high circuit complexity, high power consumption and low area utilization ratio.
The third conventional ADC system is disclosed in U.S. Pat. No. 5,675,340, which uses two-steps ADC approach, and both coarse ADC and fine ADC use an SA-ADC architecture; the required number of comparators is 2MSBs only. Thus, the third conventional ADC system has low power consumption and small chip area. However, the adder in the third conventional ADC system makes the DAC data-converting time long, thus it is not suitable for a high speed converting architecture. In addition, without adopting the subranging technique, the MSBs obtained by the coarse ADC must be transmitted to the DAC inside the SA-ADC. Accordingly, the DAC inside the SA-ADC has large circuit area (due to more unit capacitors are included herein). Besides, the DAC insides the SA-ADC has high equivalent input capacitance and slow sampling frequency.
The fourth conventional ADC system is disclosed in U.S. Pat. No. 5,247,301. Referring to FIG. 1, which is a diagram of the ADC system provided by U.S. Pat. No. 5,247,301. As shown by FIG. 1, a two-steps ADC mainly includes a high bit comparator set 1, a high bit sample/hold circuit set 2, a high bit encoder 3, a low bit comparator set 4, a low bit sample/hold circuit set 5, a low bit encoder 6, a reference voltage generator 7, a control signal generator 8 and a buffer 9.
The high bit comparator set 1 includes multiple comparators 1-1˜1-m to compare reference voltages VH-1˜VH-m with an input voltage Vin. The high bit S/H circuit set 2 includes multiple S/H circuits 2-1˜2-m, wherein each S/H circuit includes switches S2 and S21 and a capacitor Ci. The high bit S/H circuit set 2 performs sampling/holding on the input voltage Vin and sends the result to the high bit comparator set 1. The high bit encoder 3 encodes the comparison result of the high bit comparator set 1 into high bit set DoH.
Similarly, the low bit comparator set 4 includes multiple comparators 4-1˜4-n to compare reference voltages VL-1˜VL-n with the input voltage Vin. The low bit S/H circuit set 5 includes multiple S/H circuits 5-1˜5-n, wherein each S/H circuit includes switches S5 and S51 and a capacitor Ci. The low bit S/H circuit set 5 performs sampling/holding on the input voltage Vin and sends the result to the low bit comparator set 4. The low bit encoder 6 encodes the comparison result of the low bit comparator set 4 into low bit set DoL.
The reference voltage generator 7 generates high bit reference voltages VH-1˜VH-m to the high bit comparator set 1. In addition, the reference voltage generator 7 generates low bit reference voltages VL-1˜VL-n to the low bit comparator set 4.
The control signal generator 8 respectively generates control signals φm to the analog switch Sm and control signals φs to the high bit S/H circuit set 2 and the low bit S/H circuit set 5.
The analog switch Sm controls on/off status between the input voltage Vin and the high bit S/H circuit set 2 together with the low bit S/H circuit set 5.
The fourth conventional ADC architecture combines the two-steps ADC and the subranging ADC. The fourth conventional ADC architecture has high data-converting speed, but more comparators, which comes with high circuit complexity, high power consumption, low production yield and low area utilization ratio.
The fifth conventional ADC system is disclosed in U.S. Pat. No. 4,994,806, which uses a flash ADC (with high speed converting feature) to advance the ADC converting speed. SA-ADC architecture is also used to advance the ADC accuracy. Thus, the fifth conventional ADC system absorbs the advantages both of flash ADC and SA-ADC so as to enhance the overall efficiency of the ADC without additional correction circuit. However, since a residue amplifier is employed, the residue amplifier would become a bottleneck of the entire ADC system in case the ADC is operated in high converting frequency.